![]() ![]() But the D input is the Q output of another register. In a perfect situation, all of the registers see a clock edge in the same delta cycle and change the Q output of each register to the value of the D input. The significance of this come into play when you look at the simulation of a shift register. The iteration stops when there are no more signals changing and then the simulator is ready to advance time. This happens over and over again and each iteration could be considered a delta cycle. When ever a signal changes, that signal output fans out to the input of other logic that may cause other signals to change. Different languages may have different definitions of what constitutes a delta cycle, but it is basically a simulation time step without advancing physical time. ![]() All of the activity in your design, both sequential and combinational logic, evaluates on the clock edge, and time is just a bookkeeping chore between clock edges.ĭelta cycles come into play within that instantaneous moment when everything gets evaluated. However, it is much more convenient to associate a physical time period to the clock so you can display wave-forms and diagnostic reports are more human readable.Īssuming again that your RTL has no delays in its description and the only delays in your testbench are in the generation of your clock, the simulation executes exactly the same regardless of what the clock period is. In fact in a purely synchronous RTL description, you could simulate your design with out using any time, just clock cycles. ![]() Each signal change fans out to logic that causes other signals to change. The simulator only cares about changes on signals. In an event driven logic simulator, the concept of physical time is abstracted away. ![]()
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